advance information CYWB0224ABS/cywb0224abm west bridge tm astoria tm cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-11710 rev. *a revised december 7, 2007 features n-xpress? nand controller technology ? interleave up to 16 nands with 8 chip enables (ce#) for x8 or x16 slc (CYWB0224ABS) or mlc (cywb0224abm) nand flash devices. ? 4-bit error correction coding ? bad block management ? static wear leveling multimedia device support ? up to 2 sd/sdio/mmc/mmc+/ce-ata devices slim? architecture, allowing simultaneous and independent data paths between the processor and usb, and between the usb and mass storage. fully backward compatible (including pin to pin) to antioch (cywb0124ab) high speed usb at 480 mbps ? usb 2.0 compliant ? integrated usb 2.0 transceiver, smart serial interface engine ? 16 programmable endpoints flexible processor interface, which supports: ? multiplexing and nonmultiplexing address and data interface ? sram interface ? pseudo cram interface (antioch interface) ? pseudo nand flash interface ? spi (slave mode) interface ? dma slave support ultra low power, 1.8v core operation low power modes small footprint, 6x6mm vfbga supports i2c boot and processor boot selectable clock input frequencies ? 19.2 mhz, 24 mhz, 26 mhz, and 48 mhz applications cellular phones portable media players personal digital assistants portable navigation devices digital cameras pos terminals portable video recorders west bridge tm astoria tm flexible processor interface control registers uc high-speed usb 2.0 xcvr u p s slim tm access control cypress n-xpress tm engine configurable storage interface sd/sdio/ mmc+/ ce- ata block logic block diagram [+] feedback
advance information CYWB0224ABS/cywb0224abm document #: 001-11710 rev. *a page 2 of 6 functional overview the slim? architecture the simultaneous link to independent multimedia (slim) architecture allows three different interfaces (p-port, s-port and u-port) to connect t o each other independently. with this architecture, a device using astoria is connected to a pc through a usb, without disturbi ng any of the functions of the device. the device can still a ccess mass storage when the pc is synchronizing with the main processor. the slim architecture enables new usage models, in which a pc accesses a mass storage device independent of the main processor, or enumerates access to both the mass storage and the main processor at the same time. in a handset using slim architecture, t he user can do the following: use the phone as a thumb drive. download media files to the phone with all the functionalities still available on the phone. use the same phone as a modem to connect the pc to the internet. 8051 microprocessor the 8051 microprocessor embedded in astoria does basic transaction management for all tr ansactions between the p-port, s-port, and the u-port. the 8051 does not reside in the data path; it manages the path. the data path is optimized for performance. the 8051 executes firmware that supports nand, sd, sdio, mmc+, and ce-ata devices at the s-port. for the nand device, the 8051 firmware follows the smart media algorithm to support the following: physical to logical management ecc correction support wear leveling nand flash bad blocks handling configuration and status registers the west bridge astoria device includes configuration and status registers that are accessible as memory-mapped registers through the processor interface. the configuration registers allow the system to spec ify some behaviors of astoria. for example, it can mask certain status registers from raising an interrupt. the status registers conv ey the status of astoria, such as the addresses of buffers for read operations. processor interface (p-port) communication with the external processor is realized through a dedicated processor interface. th is interface is configured to support different interface standards. this interface supports multiplexing and nonmultiplexing address or data bus in both synchronous and asynchronous pseudo cram-mapped, and nonmultiplexing address or data asynchronous sram-mapped memory accesses. the interface may be configured to pseudo nand interface to support the processor?s nand interface. in addition, this interface may be configured to support the slave spi interface. this ensures straightforward electrical communi- cation with the processor, which may have other devices connected on a shared memory bus. asynchronous accesses can reach a bandwidth of up to 66.7 mbps. synchronous accesses are performed at 33 mhz across 16 bits for up to 66.7 mbps bandwidth. the memory address is decoded to access any of the multiple endpoint buffers inside astoria. these endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the usb port. the processor writes and reads into these buffers through the memory interface. access to these buffers is contro lled by using a dma protocol or using an interrupt to the main processor. these two modes are configured by the external processor. as a dma slave, astoria gener ates a dma request signal to notify the main processor that a specific buffer is ready to be read from or written to. the external processor monitors this signal and polls astoria for the specific buffers ready for a read or write operation. it then performs t he appropriate read or write operations on the buffer through the processor interface. as a result, the external processor only deals with the buffers to access a multitude of storage de vices connected to astoria. in the interrupt mode, astoria communicates important buffer status changes to the external processor using an interrupt signal. the external processor then polls astoria for the specific buffers ready for read or write, and it performs the appropriate read or write operations through the processor interface. usb interface (u-port) in accordance with the usb 2.0 specification, astoria can operate in full-speed usb mode in addition to high-speed usb. the usb interface consists of the usb transceiver. the usb interface can access and be accessed by both the p-port and the s-port. the astoria usb interface supports programmable control/bulk/interrupt/is ochronous endpoints. mass storage support (s-port) the s-port may be configured in three different modes, which simultaneously support the following: an sd/sdio/mmc+/ce-ata port and a x8 nand port two sd/sdio/mmc+/ce-ata ports up to eight chip enable (ce#) for x8 or x16 nand flash access port these configurations are controlled by the 8051 firmware. the 16-bit nand interface is used on ly when there is no other mass storage device connected to the s-port. n-xpress nand controller (s-port) astoria, as part of its mass storage management functions, can fully manage the slc and mlc nand flash devices. the embedded 8051 manages the actual reading and writing of the nand, along with its required prot ocols. it performs standard nand management functions, such as ecc and wear leveling. the astoria supports single bit ecc for the slc and 4-bit ecc for mlc nand flash. slc nand flash devices are supported by cywb0244abs. cywb0244abm su pports both slc and mlc nand flash devices. [+] feedback
advance information CYWB0224ABS/cywb0224abm document #: 001-11710 rev. *a page 3 of 6 sd/sdio/mmc+/ce-ata port (s-port) when astoria is configured through firmware to support sd/sdio/mmc+/ce-ata, this interface supports the following: the multimedia card system sp ecification, mmca technical committee, version 4.1. sd memory card specification - part 1, physical layer specification, sd group, ve rsion 1.10, october 15, 2004. sd memory card specification - part 1, physical layer specification, sd group, version 2.0, may 9, 2006. sd specifications - part e1 sd io specification, version 1.10, august 18, 2004. ce-ata specification - ce-ata digital protocol, ce-ata committee, version 1.1, september, 2005 west bridge astoria provides support for 1-bit and 4-bit sd and sdio cards; 1-bit, 4-bit and 8-bit mmc; mmc+ cards, and ce-ata drive. for the sd, sdio, mmc/mmc plus, and ce-ata, this block supports one card for one physical bus interface. astoria supports sd commands including the multisector program command, which is handled by api. table 1. astoria pin assignments pin name io pin description power domain non-multiplexing multiplexing sram pnand spi p-port clk clk ext pull up sck i clock/spi clock pvddq vgnd ce# ce# ce# cs# ss# i chip enable/nand chip select/spi slave select a0 ext pull up a0 cle# ext pull up i address bus 0/pnand command latch a1 ext pull up a1 rb# ext pull up io address bus 1/pn and ready_buy a[3:2] set a[3:2] = 01 a[3:2] set a[3:2] = 00 set a[3:2] = 10 i addr. bus [3:2] a4 ext pull up a4 wp# ext pull up i addr. bus 4/nand write protect a5 scl a5 scl scl io address bus 5/i2c clock a6 sda a6 sda sda io address bus 6/i2c data a7] ext pull up a7 set a7 to 0 - lbd set a7 to 1 - sbd ext pull up i addr. bus 7 dq[0] ad[0] dq[0] io[0] sdi io spi input/data bus 0 dq[1] ad[1] dq[1] io[1] sdo io spi output/data bus 1 dq[15:2] ad[15:2] dq[15:2] io[15:2] ext pull up io data bus adv# adv# ale# ext pull up i address valid oe# oe# oe# re# ext pull up i output enable we# we# we# we# ext pull up i write enable int# int# int# int# sint o interrupt request drq# drq# drq# drq# n/c o dma request dack# dack# dack# dack# ext pull up i dma acknowledgement u-port d+ io/z usb d+ uvddq uvssq d- io/z usb d- uvalid o external usb switch control [+] feedback
advance information CYWB0224ABS/cywb0224abm document #: 001-11710 rev. *a page 4 of 6 s-port sdio and nand configuration nand only configuration dual sdio configuration nand and gpio configuration sdio and gpio configuration sd_d[7:0] nand_io[15:8] / pd[7:0] (gpio) sd_d[7:0] nand_io[15:8] / pd[7:0] (gpio) sd_d[7:0] io sd data bus/nand upper io bus ssvddq vgnd sd_clk nand_ce8#/n and_r/b4# sd_clk pc-7 (gpio) / nand_ce8# / nand_r/b4# sd_clk io sd clock/nand ce8#/nand r/b4# sd_cmd nand_ce7#/n and_r/b3# sd_cmd pc-3 (gpio) / nand_ce7# / nand_r/b3# sd_cmd io sd command, nand ce7#, or nand_r/b3# sd_pow nand_ce6# sd_pow pc-6 (gpio) / nand_ce6# sd_pow io sd power control/nand ce6# sd_wp nand_ce5# sd_wp pc-1 (gpio) / nand_ce5# sd_wp io gpio (sd write protection microswitch) or nand ce5# nand_io[7:0] nand_io[7:0] sd2_d[7:0] nand_io[7:0] pb[7:0] (gpio) io nand lower io bus/2 nd sd data bus snvddq vgnd nand_cle nand_cle sd2_clk nand_cle pa-6 (gpio) io cmd latch enable/2 nd sd clock nand_ale nand_ale sd2_cmd nand_ale pa-7 (gpio) io address latch enable/2 nd sd cmd nand_ce# nand_ce# sd2_pow nand_ce# pc-0 (gpio) io chip enable/2 nd sd power control nand_re# nand_re# n/c nand_re# n/c o read enable nand_we# nand_we# n/c nand_we# n/c o write enable nand_wp# nand_wp# pa-5 (gpio) nand_wp# pa-5 (gpio) io write protect nand_r/b# nand_r/b# nand_r/b# i ready/busy/2 nd sd wp nand_ce2# nand_ce2# sd2_wp nand_ce2# pc-2 (gpio) io chip enable 2 other resetout / nand_r/b2# nand_r/b2# resetout nand_r/b2# / resetout resetout io reset out/nand busy/ready gvddq vgnd gpio[0] / sd_cd / nand_ce4# nand_ce4# pc-4 (gpio[0]) / sd_cd pc-4 (gpio[0]) / nand_ce4# pc-4 (gpio[0]) / sd_cd io general input/output 0 or sd/mmc card detection or nand ce4# gpio[1] / nand_ce3# nand_ce3# pc-5 (gpio[1]) / sd2_cd pc-5 (gpio[1]) / nand_ce3# pc-5 (gpio[1]) io general input/output 1 or nand ce3# reset# i reset wakeup i wake up signal xtalin i crystal/clock in xvddq vgnd xtalout o crystal out config xtalslc[1:0] i clock select 0 and 1 gvddq vgnd nandcfg i s port configuration test[2:0] i test configuration power pvddq pwr processor interface vdd snvddq pwr nand vdd uvddq pwr usb vdd ssvddq pwr sdio vdd gvddq pwr miscellaneous io vdd avddq pwr analog vdd xvddq pwr crystal vdd vdd pwr core vdd vdd33 pwr independent 3.3v nominal uvssq pwr usb gnd avssq pwr analog gnd vgnd pwr core gnd table 1. astoria pin assignments (continued) pin name io pin description power domain non-multiplexing multiplexing sram pnand spi [+] feedback
advance information CYWB0224ABS/cywb0224abm document #: 001-11710 rev. *a page 5 of 6 ordering information package diagram ordering code package type nand flash support available clock input frequencies (mhz) CYWB0224ABS-bvxi 100 vfbga ? pb-free support slc nand fl ash only 19.2, 24, 26, 48 cywb0224abm-bvxi 100 vfbga ? pb-free support slc and mlc nand flash 19.2, 24, 26, 48 figure 1. 100 vfbga (6 x 6 x 1.0 mm) bz100a ! ! # / 2 . % 2 ? ? 8 ? - # ! " ? - # " ! 8 ? - ! 8 # 3 % ! 4 ) . ' 0 , ! . % 2 % & # # ! # / 2 . % 2 4 / 0 6 ) % 7 " / 4 4 / - 6 ) % 7 " # $ % & ' ( ? ? ! ? ? " 2 % & * 2 % & % 2 % . # % * % $ % # - /
# 0 + ' 7 % ) ' ( 4 4 " $ . % 7 0 + ' + ' + * ( $ & % # " ! 51-85209 *b [+] feedback
document #: 001-11710 rev. *a revised december 7, 2007 page 6 of 6 west bridge and antioch are trademarks of cypress semiconductor corporation. all other trademarks or registered trademarks refe renced herein are the property of their respective owners. advance information CYWB0224ABS/cywb0224abm ? cypress semiconductor corporation, 2007. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: CYWB0224ABS/cywb0224abm west bridge tm astoria tm document number: 001-11710 rev. ecn no. issue date orig. of change description of change ** 567055 see ecn vso new data sheet *a 1830226 see ecn vso/aesa in the feature list, adding t he bullets of ?n-xpress controller technology? and ?multimedia device support? in the feature list, removed the bullet of ?mass storage device support? update the bullet of application update logic block diagram. updated the section of ?nand port? to n-xpress nand controller? updated the pin assignment table fix the typo of vgan in pin assignment table [+] feedback
|
